#  Simulation Model Generator
#  Xilinx EDK 14.4 EDK_P.49d
#  Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
#
#  File     mem_bus_mux_0_wave.tcl (Wed May 22 15:07:26 2013)
#
#  Module   system_mem_bus_mux_0_wrapper
#  Instance mem_bus_mux_0
#  Because EDK did not create the testbench, the user
#  specifies the path to the device under test, $tbpath.
#
if { [info exists PathSeparator] } { set ps $PathSeparator } else { set ps "/" }
if { ![info exists tbpath] } { set tbpath "${ps}system" }

  wave add $tbpath${ps}mem_bus_mux_0${ps}ADDR_RAM_IN -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_O_RAM -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_T_RAM -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_I_RAM -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}BEN_RAM_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}CEN_RAM_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}OEN_RAM_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}WEN_RAM_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}ADDR_FLASH_IN -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_O_FLASH -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_T_FLASH -into $id
# wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_I_FLASH -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}RPN_FLASH_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}CEN_FLASH_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}OEN_FLASH_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}WEN_FLASH_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}C_QUAD_SPI_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}S_QUAD_SPI_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_O_QUAD_SPI -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_T_QUAD_SPI -into $id
# wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_I_QUAD_SPI -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}MEM_ADDR -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_T -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}DQ_I -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}MEM_OEN -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}MEM_WEN -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}RAM_CEN_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}RAM_BEN_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}FLASH_ADDR -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}FLASH_CEN_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}FLASH_RPN_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}QUAD_SPI_C_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}QUAD_SPI_S_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}MOSI_QUAD_SPI_O -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}MOSI_QUAD_SPI_T -into $id
  wave add $tbpath${ps}mem_bus_mux_0${ps}MOSI_QUAD_SPI_I -into $id

